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| HM5116405B Series HM5117405B Series 4,194,304-word x 4-bit Dynamic Random Access Memory ADE-203-511A (Z) Rev. 1.0 Mar. 28, 1996 Description The Hitachi HM5116405B Series, HM5117405B Series are CMOS dynamic RAMs organized 4,194,304word x 4-bit. They employ the most advanced CMOS technology for high performance and low power. The HM5116405B Series, HM5117405B Series offer Extended Data Out (EDO) Page Mode as a high speed access mode. Features * Single 5 V (10%) * High speed Access time: 60 ns/70 ns/80 ns (max) * Low power dissipation Active mode : 550mW/495 mW/440 mW (max) (HM5116405B Series) : 605mW/550 mW/495 mW (max) (HM5117405B Series) Standby mode : 11 mW (max) :0.83 mW (max) (L-version) * EDO page mode capability * Long refresh period 4096 refresh cycles : 64 ms (HM5116405B Series) : 128 ms (L-version) 2048 refresh cycles : 32 ms (HM5117405B Series) : 128 ms (L-version) * 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh * Battery backup operation (L-version) This specification is fully compatible with the 16-Mbit DRAM specifications from TEXAS INSTRUMENTS. HM5116405B Series, HM5117405B Series * Test function 16-bit parallel test mode Ordering Information Type No. HM5116405BS-6 HM5116405BS-7 HM5116405BS-8 HM5116405BLS-6 HM5116405BLS-7 HM5116405BLS-8 HM5117405BS-6 HM5117405BS-7 HM5117405BS-8 HM5117405BLS-6 HM5117405BLS-7 HM5117405BLS-8 HM5116405BTS-6 HM5116405BTS-7 HM5116405BTS-8 HM5116405BLTS-6 HM5116405BLTS-7 HM5116405BLTS-8 HM5117405BTS-6 HM5117405BTS-7 HM5117405BTS-8 HM5117405BLTS-6 HM5117405BLTS-7 HM5117405BLTS-8 Access time 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 300-mil 26-pin plastic TSOP II (TTP-26/24DA) Package 300-mil 26-pin plastic SOJ (CP-26/24DB) 2 HM5116405B Series, HM5117405B Series Pin Arrangement HM5116405BS/BLS Series HM5116405BTS/BLTS Series VCC I/O1 I/O2 WE RAS A11 1 2 3 4 5 6 26 25 24 23 22 21 VSS I/O4 I/O3 CAS OE A9 VCC I/O1 I/O2 WE RAS A11 1 2 3 4 5 6 26 25 24 23 22 21 VSS I/O4 I/O3 CAS OE A9 A10 A0 A1 A2 A3 V CC 8 9 10 11 12 13 19 18 17 16 15 14 (Top view) A8 A7 A6 A5 A4 VSS A10 A0 A1 A2 A3 V CC 8 9 10 11 12 13 19 18 17 16 15 14 (Top view) A8 A7 A6 A5 A4 VSS Pin Description Pin name A0 to A11 Function Address input -- Row/Refresh address A0 to A11 -- Column address A0 to A9 Data input/Data output Row address strobe Column address strobe Write enable Output enable Power supply Ground I/O1 to I/O4 RAS CAS WE OE VCC VSS 3 HM5116405B Series, HM5117405B Series Pin Arrangement HM5117405BS/BLS Series HM5117405BTS/BLTS Series VCC I/O1 I/O2 WE RAS NC 1 2 3 4 5 6 26 25 24 23 22 21 VSS I/O4 I/O3 CAS OE A9 VCC I/O1 I/O2 WE RAS NC 1 2 3 4 5 6 26 25 24 23 22 21 VSS I/O4 I/O3 CAS OE A9 A10 A0 A1 A2 A3 V CC 8 9 10 11 12 13 19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS A10 A0 A1 A2 A3 V CC 8 9 10 11 12 13 19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS (Top view) (Top view) Pin Description Pin name A0 to A10 Function Address input -- Row/Refresh address A0 to A10 -- Column address A0 to A10 Data input/Data output Row address strobe Column address strobe Write enable Output enable Power supply Ground No connection I/O1 to I/O4 RAS CAS WE OE VCC VSS NC 4 HM5116405B Series, HM5117405B Series Block Diagram RAS I/O 4 I/O Buffer 4 CAS WE OE I/O 3 I/O Buffer 3 Column decoder & driver Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus Peripheral circuit Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus Selector Selector Selector Row decoder & driver Row decoder & driver Selector Column decoder & driver Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus Row decoder & driver Selector Selector I/O Buffer 1 I/O 1 I/O Buffer 2 I/O 2 Address A0 to A11: HM5116405B Address A0 to A10: HM5117405B Selector Selector Row decoder & driver 5 HM5116405B Series, HM5117405B Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Input high voltage Input low voltage Note: Symbol VCC VIH VIL Min 4.5 2.4 -1.0 Typ 5.0 -- -- Max 5.5 6.5 0.8 Unit V V V Note 1 1 1 1. All voltage referred to VSS . 6 HM5116405B Series, HM5117405B Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) (HM5116405B Series) HM5116405B -6 Parameter Operating current* , * 2 1 -7 -8 Symbol Min Max Min Max Min Max Unit Test conditions I CC1 I CC2 -- -- 80 2 -- -- 70 2 -- -- 65 2 mA t RC = min mA TTL interface RAS, CAS = VIH Dout = High-Z mA CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z Standby current -- 1 -- 1 -- 1 Standby current (L-version) RAS-only refresh current*2 Standby current* 1 I CC2 -- 150 -- 150 -- 150 A I CC3 I CC5 -- -- 80 5 -- -- 70 5 -- -- 65 5 mA t RC = min mA RAS = VIH CAS = VIL Dout = enable mA t RC = min mA t HPC = min CMOS interface Dout = High-Z, CBR refresh: tRC = 31.3 s t RAS 0.3 s 0 V Vin 7 V 0 V Vin 7 V Dout = disable High Iout = -2 mA Low Iout = 2 mA CAS-before-RAS refresh current EDO page mode current*1, * 3 Battery backup current I CC6 I CC7 I CC10 -- -- -- 80 -- 70 90 -- -- 65 80 100 -- 350 -- 350 -- 350 A Input leakage current Output leakage current Output high voltage Output low voltage I LI I LO VOH VOL -10 10 -10 10 2.4 0 -10 10 -10 10 -10 10 -10 10 A A VCC 2.4 0.4 0 VCC 2.4 0.4 0 VCC V 0.4 V Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 7 HM5116405B Series, HM5117405B Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) (HM5117405B Series) HM5117405B -6 Parameter Operating current* , * 2 1 -7 -8 Symbol Min Max Min Max Min Max Unit Test conditions I CC1 I CC2 -- -- 110 -- 2 -- 100 -- 2 -- 90 2 mA t RC = min mA TTL interface RAS, CAS = VIH Dout = High-Z mA CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z Standby current -- 1 -- 1 -- 1 Standby current (L-version) RAS-only refresh current*2 Standby current* 1 I CC2 -- 150 -- 150 -- 150 A I CC3 I CC5 -- -- 110 -- 5 -- 100 -- 5 -- 90 5 mA t RC = min mA RAS = VIH CAS = VIL Dout = enable mA t RC = min mA t HPC = min CMOS interface Dout = High-Z, CBR refresh: tRC = 62.5 s t RAS 0.3 s 0 V Vin 7 V 0 V Vin 7 V Dout = disable High Iout = -2 mA Low Iout = 2 mA CAS-before-RAS refresh current EDO page mode current*1, * 3 Battery backup current I CC6 I CC7 I CC10 -- -- -- 110 -- 110 -- 350 -- 100 -- 100 -- 350 -- 90 90 350 A Input leakage current Output leakage current Output high voltage Output low voltage I LI I LO VOH VOL -10 10 -10 10 2.4 0 -10 10 -10 10 -10 10 -10 10 A A VCC 2.4 0.4 0 VCC 2.4 VCC V 0.4 0 0.4 V Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 8 HM5116405B Series, HM5117405B Series Capacitance (Ta = 25C, VCC = 5 V 10%) Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. 9 HM5116405B Series, HM5117405B Series AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) *1, *2, *18 Test Conditions * * * * * Input rise and fall time: 2 ns Input levels: VIL = 0 V, V IH = 3 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5116405B/HM5117405B -6 Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Symbol Min Max t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT 104 -- 40 10 60 10 0 10 0 10 20 15 15 48 5 15 0 0 2 -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- -- -- -- 50 -7 Min Max 124 -- 50 13 70 13 0 10 0 13 20 15 18 58 5 18 0 0 2 -- -- 10000 10000 -- -- -- -- 52 35 -- -- -- -- -- -- 50 -8 Min Max 144 -- 60 15 80 15 0 10 0 15 20 15 20 68 5 20 0 0 2 -- -- 10000 10000 -- -- -- -- 60 40 -- -- -- -- -- -- 50 Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 3 4 10 HM5116405B Series, HM5117405B Series Read Cycle HM5116405B/HM5117405B -6 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time Symbol Min Max t RAC t CAC t AA t OEA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD -- -- -- -- 0 0 60 0 30 18 0 3 3 -- -- 15 3 -- -- 15 15 60 15 30 15 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -7 Min Max -- -- -- -- 0 0 70 0 35 23 0 3 3 -- -- 18 3 -- -- 18 18 70 18 35 18 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -8 Min Max -- -- -- -- 0 0 80 0 40 28 0 3 3 -- -- 20 3 -- -- 20 20 80 20 40 20 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 13 5 12 12 8, 9, 19 9, 10, 17, 19 9, 11, 17, 19 9, 19 11 HM5116405B Series, HM5117405B Series Write Cycle HM5116405B/HM5117405B -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol Min Max t WCS t WCH t WP t RWL t CWL t DS t DH 0 10 10 10 10 0 10 -- -- -- -- -- -- -- -7 Min Max 0 13 10 13 13 0 13 -- -- -- -- -- -- -- -8 Min Max 0 15 10 15 15 0 15 -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns 15 15 14 Read-Modify-Write Cycle HM5116405B/HM5117405B -6 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min Max t RWC t RWD t CWD t AWD t OEH 149 -- 82 37 52 15 -- -- -- -- -7 Min Max 175 -- 95 43 60 18 -- -- -- -- -8 Min Max 199 -- 107 -- 47 67 20 -- -- -- Unit Notes ns ns ns ns ns 14 14 14 Refresh Cycle HM5116405B/HM5117405B -6 Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol Min Max t CSR t CHR t WRP t WRH t RPC 5 10 0 10 0 -- -- -- -- -- -7 Min Max 5 10 0 10 0 -- -- -- -- -- -8 Min Max 5 10 0 10 0 -- -- -- -- -- Unit Notes ns ns ns ns ns 12 HM5116405B Series, HM5117405B Series EDO Page Mode Cycle HM5116405B/HM5117405B -6 Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low CAS hold time referred OE CAS to OE setup time Read command hold time from CAS precharge Symbol Min Max t HPC t RASP t CPA t CPRH t DOH t COL t COP t RCHC 25 -- -- 35 3 10 5 35 -- -7 Min Max 30 -- -8 Min Max 35 -- Unit Notes ns 20 16 9, 17, 19 100000 -- 35 -- -- -- -- -- -- 40 3 13 5 40 100000 -- 40 -- -- -- -- -- -- 45 3 15 5 45 100000 ns 45 -- -- -- -- -- ns ns ns ns ns ns 9, 17 EDO Page Mode Read-Modify-Write Cycle HM5116405B/HM5117405B -6 Parameter EDO page mode read- modify-write cycle time WE delay time from CAS precharge Symbol Min Max t HPRWC t CPW 79 54 -- -- -7 Min Max 90 62 -- -- -8 Min Max 99 69 -- -- Unit Notes ns ns 14 Test Mode Cycle *18 HM5116405B/HM5117405B -6 Parameter Test mode WE setup time Test mode WE hold time Symbol Min Max t WTS t WTH 0 10 -- -- -7 Min Max 0 10 -- -- -8 Min Max 0 10 -- -- Unit Notes ns ns Refresh (HM5116405B Series) Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 64 128 Unit ms ms Notes 4096 cycles 4096 cycles 13 HM5116405B Series, HM5117405B Series Refresh (HM5117405B Series) Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 32 128 Unit ms ms Notes 2048 cycles 2048 cycles Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M x4 are don't care during test mode. Test mode is set by performing a WE-and-CAS-before-RAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. 14 HM5116405B Series, HM5117405B Series To get out of test mode and enter a normal operation mode, perform either a regular CASbefore-RAS refresh cycle or RAS-only refresh cycle. 19. In a test mode read cycle, the value of tRAC , t AA , t CAC and t CPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. XXX: H or L (H: V IH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout 15 HM5116405B Series, HM5117405B Series Timing Waveforms*21 Read Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t RAD t ASR t ASC t RAL t CAL t CAH t RAH Address Row Column t RRH t RCHR t RCS t RCH WE t WED t DZC t CDD t RDD Din High-Z t DZO t OEA t OED OE t OEZ t OHO t OFF t OH t OFR t OHR t WEZ Dout Dout t CAC t AA t RAC t CLZ 16 HM5116405B Series, HM5117405B Series Early Write Cycle t RC t RAS t RP RAS t CSH t RCD tT CAS t RSH t CAS t CRP t ASR t RAH t ASC t CAH Address Row Column t WCS t WCH WE t DS t DH Din Din Dout High-Z** * OE : H or L ** t WCS t WCS (min) 17 HM5116405B Series, HM5117405B Series Delayed Write Cycle t RC t RAS t RP RAS t CSH t RCD tT CAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP Address Row Column t CWL t RCS t RWL t WP WE t DZC t DS t DH Din High-Z Din t OEH t OED t DZO OE t OEZ t CLZ Dout High-Z Invalid Dout 18 HM5116405B Series, HM5117405B Series Read-Modify-Write Cycle t RWC t RAS t RP RAS tT t RCD t CAS t CRP CAS t RAD t ASR t RAH t ASC t CAH Address Row t RCS Column t CWD t AWD t RWD tCWL t RWL t WP WE t DZC t DS Din High-Z Din t DH t DZO t OED t OEA t OEH OE t CAC t AA t RAC t OEZ t OHO High-Z Dout t CLZ Dout 19 HM5116405B Series, HM5117405B Series RAS-Only Refresh Cycle t RC t RAS RAS tT t CRP CAS t RPC t CRP t RP t ASR Address t OFR t OFF Dout Row t RAH High-Z * OE, WE: H or L 20 HM5116405B Series, HM5117405B Series CAS-Before-RAS Refresh Cycle t RC t RP RAS t RPC CAS t CSR tT t CHR t RPC t CRP t RAS t RP , t CP t WRP t WRH t CP WE Address t OFR t OFF Dout High-Z ** OE: H or L 21 HM5116405B Series, HM5117405B Series Hidden Refresh Cycle t RC t RAS t RC t RAS t RC t RP t RAS t RP t RP RAS tT t RSH t RCD CAS t CHR t CRP t RAD t ASR t RAH Address Row t ASC t RAL t CAH Column t RRH t RCH WE t DZC High-Z Din t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout t RCS t RRH t WRH t WRP t WRP tWRH t WED t CDD t RDD t OED t OFF t OH t OEZ t WEZ t OHO t OFR t OHR 22 HM5116405B Series, HM5117405B Series EDO Page Mode Read Cycle t RP RAS t RASP tT t CSH t CAS t RCS t RCHR t RCH t RCS t CP t HPC t CAS t CP t HPC tCAS t RCHC t HPC t CPRH t CP t t CRP RSH CAS tCAS t RRH t RCH WE tASR Address tRAH tASC Row tCAH t ASC t CAH Column 2 t CAL t ASC t CAH Column 3 t CAL tASC t RAL t CAH Column 4 t WED Column 1 t CAL tDZC t CAL tRDD tCDD Din High-Z tDZO tCOL tCOP tOED OE tOEA tCPA tCPA tCAC tAA tAA tCAC tOEZ tWEZ tOHO tCPA tAA tCAC tAA tOEZ tOFR tOHR tOEZ tCAC tRAC tOEA tDOH tOHO tOEA tOHO tOFF tOH Dout Dout 1 Dout 2 Dout 2 Dout 3 Dout 4 23 HM5116405B Series, HM5117405B Series EDO Page Mode Early Write Cycle t RASP t RP RAS tT t CSH t RCD t CAS CAS t CP t HPC t CAS t CP t RSH t CAS t CRP t ASR t RAH t ASC t CAH t ASC tCAH t ASC t CAH Address Row Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS t DH t DS t DH t DS t DH Din Din 1 Din 2 Din N Dout High-Z** * OE : H or L ** t WCS t WCS (min) 24 HM5116405B Series, HM5117405B Series EDO Page Mode Delayed Write Cycle t RASP t RP RAS tT t CSH t RCD CAS t CP t CAS t HPC t CAS t CP t RSH t CAS t CRP t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z Invalid Dout Invalid Dout Invalid Dout 25 HM5116405B Series, HM5117405B Series EDO Page Mode Read-Modify-Write Cycle t RASP t RP RAS tT t CP t RCD CAS t HPRWC t CP t CAS t CAS t RSH t CAS t CRP t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO t OED t ASC t CAH Column 2 t CWL t RCS t CPW t AWD t CWD t RCS t CWL t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL Address t WP t DZC t DS t DH Din 2 t OED t OEH t DZO t OED t WP t DZC t DS t DH Din N Din 1 t DZO t OEH t OEH * OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ High-Z Dout Dout 1 Dout 2 Dout N 26 HM5116405B Series, HM5117405B Series EDO Page Mode Mix Cycle (1) t RP RAS t RASP t CRP tCAS tRSH t RCS tCPW tAWD t ASC tRAH Row tCAH t ASC t CAH Column 2 t CAL tASC t CAH Column 3 t CAL t DS High-Z tOED t DH Din 3 tWED tWP t RAL t CAH Column 4 t CAL tRDD tCDD t RCS t RRH t RCH tT CAS t CP t CAS t CSH t RCD t WCS t WCH t CAS t CP tCAS t CP WE tASR Address tASC Column 1 t CAL t DS Din t DH Din 1 OE tCPA tAA tOEA tCPA tCPA tAA t OEZ tAA tOFR tWEZ tOEZ tCAC tOHO tOFF tOH tCAC t DOH tCAC t OHO tOEA Dout Dout 2 Dout 3 Dout 4 27 HM5116405B Series, HM5117405B Series EDO Page Mode Mix Cycle (2) t RP RAS t RASP tT CAS t CSH t CAS t RCD t RCS t RCHR t CP t CAS t CP tCAS t CP tCAS t RCS tCPW tWP t RAL tASC t CAH Column 4 t CAL t DS t DH Din 3 tOED tCOP tRSH t CRP t RCH tWCS t WCH t RCS t RRH t RCH WE tASR Address tRAH Row t ASC tCAH t ASC t CAH Column 2 t CAL t DS t DH Din 2 tOED tCOL t ASC t CAH Column 3 t CAL Column 1 t CAL tRDD tCDD Din High-Z tWED OE tAA tOEA tCAC tRAC t OHO Dout t OEA tOEZ tCPA tAA tCAC tOEZ t OHO Dout 3 tCPA tAA tCAC tOEA tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4 Dout 1 28 HM5116405B Series, HM5117405B Series Test Mode Cycle *18 Set Cycle** Test Mode Cycle *,** Reset Cycle Normal Mode RAS CAS WE * CBR or RAS-only refresh ** Address, Din, OE: H or L 29 HM5116405B Series, HM5117405B Series Test Mode Set Cycle t RC t RP t RAS t RP RAS tT CAS t CP t WTS t WTH WE Address t OFR t OFF Dout High-Z 30 SP C@ ,, S R P C B @ t CP t RPC t CSR t CHR t RPC t CRP HM5116405B Series, HM5117405B Series Package Dimensions HM5116405BS/BLS Series HM5117405BS/BLS Series (CP-26/24DB) Unit: mm 26 16.90 17.27 Max 21 19 14 7.62 0.13 1 68 0.74 13 8.51 0.13 3.50 0.26 1.3 Max 0.43 0.10 0.10 1.27 0.63 Min 6.71 0.25 HM5116405BTS/BLTS Series HM5117405BTS/BLTS Series (TTP-26/24DA) 2.65 0.12 Unit: mm 26 17.14 17.54 Max 21 19 14 1 68 1.27 0.21 M 13 9.22 0.2 0 - 5 0.40 0.10 7.62 1.20 Max 0.10 1.15 Max 0.145 -0.025 0.08 Min 0.18 Max 0.68 0.50 0.10 +0.075 31 HM5116405B Series, HM5117405B Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 32 HM5116405B Series, HM5117405B Series Revision Record Rev. 0.0 1.0 Date Feb. 11, 1996 Mar. 28, 1996 Contents of Modification Initial issue Unification of HM5116405B and HM5117405B Series Drawn by J. Miyake Approved by K. Hayakawa Pin Descriptions Addition of Row/Refresh address and Column address to address input Timing Waveforms Deletion of notes for RAS-only refresh cycle 33 |
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